Postdoctoral Research Felllow in FPGAs and Networks

King Abdullah University of Science and Technology
May 15, 2024
Offerd Salary:Negotiation
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Contract Type:Other
Working Time:Negotigation
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King Abdullah University of Science and Technology: Postdoc Positions:

Computer, Electrical and Mathematical Science and Engineering Division (postdoc): Computer Science and Electrical Engineering (postdoc)


King Abdullah University of Science and Technology, Saudi Arabia

Open Date

Dec 01, 2022


We invite applications for a Postdoctoral Research Fellow position in the Accelerated Connected Computing Lab (ACCL) at KAUST to work at the intersection of FPGA acceleration and networked systems. The research project explores approaches for integrating accelerators into network infrastructure with lightweight interfaces and virtualisation. You will develop methodologies, software infrastructure, and hardware frameworks to enable hardware acceleration in a new networked paradigm. You will work with PIs (Suhaib Fahmy and Marco Canini) and PhD students in ACCL to achieve high impact research output. You will have access to our well-equipped FPGA acceleration testbed, as well as addition high performance computing resources as needed. Through interactions with the wider group, you will have the opportunity to contribute to wider projects in the Computing Systems area.

KAUST offers you the opportunity to pursue world-class research among a highly diverse student/postdoc population of high achievers, and interaction with world-leading faculty across a range of disciplines. Postdocs at KAUST enjoy generous salaries and free accommodation and healthcare on a world class campus with ample recreational facilities and a private beach.


Applicants must have a PhD in Computer Engineering, Computer Science, or Electrical and Computer Engineering, and have published their research in prestigious conferences and journals in related topics.

Candidates should have some experience working with FPGAs as well as an understanding of computer networks. Experience with both RTL and HLS design is favoured. The ideal candidate would have some experience working with FPGA- based networking platforms/frameworks such as NetFPGA, Corundum, Xilinx OpenNIC, or the ETHZ HLS TCP/IP Stack. Familiarity with Software Defined Networking, SmartNICs, RDMA is an advantage.

Application Instructions

Applicants can contact the PI, Suhaib Fahmy, at [email protected], with questions in advance of applying.

This position is offered for one year initially, renewable up to three years.

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