Collider experiments require challenging detectors and data acquisition electronics. The PANDA experiment, currently under construction at GSI in Darmstadt, will be one of the major experiments at the Facility for Antiproton and Ion Research (FAIR). The PANDA collaboration, with more than 400 scientists from 18 countries, intends to do elementary physics research on various topics like weak and strong forces, exotic states of matter and the structure of hadrons. The PANDA detector is composed of several detector layers. The detector closest to the interaction point, designed for precise reconstruction of primary and secondary vertices of the interaction, is the Micro Vertex Detector (MVD). It is made of silicon pixel and microstrip sensors and it will use custom front-end electronics to readout the data. Each microstrip detector module will be equipped with front-end chips as well as one digital Module Data Concentrator (MDC) ASIC. The MDC serves as link between the frontend chips and the data acquisition (DAQ) system. The chip will be placed on the detector module inside the active area. It will read out one double-sided strip sensor by multiplexing the data stream of all front- ends chips. Besides the readout, the MDC ASIC will also decode and multiplex the front-end chip data, implements the data transmission to the DAQ system via serial LpGBT/XGBT links and provides slow control functions (parameter settings, monitoring).Organizational unit
Institute for Data Processing and Electronics (IPE)Job description
This PhD thesis will focus on the design and development of the MDC ASIC for the local control of the microstrip detector modules of PANDA. Since it will be located in the same radiation environment as the front-end chips, Single Event Upset (SEU) mitigation techniques like triple redundancy will be employed for all critical components. To satisfy the requirements on radiation-hardness, the chip will be developed in 110 nm UMC CMOS technology.
The PhD project pursues the following objectives:
There are many aspects of this project, which all require in-depth R&D. This includes advanced design and production of complex digital ASICs for modern microstrip detectors, the implementation of radiation tolerant logic and of high-speed communications, etc. The PhD project will be carried out at the Institute of Data Processing and Electronics (IPE) at KIT. Commissioning will require regular trips to GSI. The research plan includes the design of electronics, test & validation, and commissioning at the PANDA detector. Throughout the project the results will be presented to the PANDA collaboration. Supervision of bachelor and master students, presentations at scientific conferences, and publication in high-impact journals is expected.Starting date
ab sofort / as soon as possiblePersonal qualification
A master degree in Electrical Engineering, physics or equivalent is required. Experience in FPGA design is an advantage, as well as being comfortable in specifying system components and sound skills to solve technical problems. You are a naturally curious person who is eager to learn fast and has a strong interest in research. Good English language proficiency is essential, basic German language skills are of advantage.Salary
Salary category 13, depending on the fulfillment of professional and personal requirements.Contract duration
limited to 3 yearsApplication up to
March 04, 2023.Contact person in line-management
For further information, please contact Mr. Dr. Caselle, phone +49 721 608-25903.
Please apply online using the button below for this vacancy number 01/2023.
We prefer to balance the number of employees (f/m/d). Therefore we kindly ask female applicants to apply for this job. Recognized severely disabled persons will be preferred if they are equally qualified.Contact
Personnel Support is provided by: Personalservice (PSE) - Human Resources Ms Ahmed Phone: +49 721 608-25006,
Hermann-von-Helmholtz-Platz 1, 76344 Eggenstein-Leopoldshafen, Germany