Post-Doctoral Research Visit F/M Security of Emerging On-Chip Interconnects

2023-05731 - Post-Doctoral Research Visit F/M Security of Emerging On-Chip Interconnects

Contract type : Fixed-term contract

Renewable contract : Oui

Level of qualifications required : PhD or equivalent

Fonction : Post-Doctoral Research Visit

About the research centre or Inria department

The Inria Rennes - Bretagne Atlantique Centre is one of Inria's eight centres and has more than thirty research teams. The Inria Center is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc.

Context

This postdoc position will be funded by the Rakes and AllOpticall2 ANR Projects. These projects involve Inria Taran (Rennes/Lannion), INL (Lyon), Lab-STICC (Lorient), and TIMA (Grenoble).

The Taran team has already a strong background in on-chip interconnects, and on the emerging interconnect paradigms (WiNoC, ONoC) targeted in this project.

Assignment

Subject

Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for high-performance embedded computing systems and HPC.

To satisfy the increase of on-chip communication requirements of theses architectures 1, technology evolution has allowed for the integration of silicon photonics and wireless communications on chip, thus leading to Wireless Network-on-Chip (WiNoC) 2-3 and Optical Network-on-Chip (ONoC) 4-5 paradigms.

As technology advances and the use of emerging on-chip interconnects increases, the need for secure design and implementation becomes increasingly criticial 6. Indeed, as on-chip interconnects are used to transfer data and instructions between different components within a system-on-a-chip (SoC), these interconnects are vulnerable to a variety of attacks, such as side-channel attacks and fault injection attacks, which can compromise the security of the entire system. As a result, securing on-chip interconnects is becoming an important design concern for developers and manufacturers of SoCs. This includes implementing security measures such as encryption, and fault tolerance to protect against potential threats and maintain the integrity of the system.

The scope of the PostDoc position is relatively open and applicants are expected to identify the direction that suits them the most as a function of their background and interest. The goal is to improve the security of emerging on-chip interconnects in the context of manycore architectures.

Bibliography:

Karkar et al. “A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many- Cores”. In: IEEE Circuits and Systems Magazine 16., pp. 58–72 , 2016.

F. Chang, et al., “CMP Network-on-Chip Overlaid with Multi-Band RF- Interconnect,” Proc. of IEEE Int. symposium on High- Performance Computer Architecture (HPCA), pp. 191-202, 2008.

Ortiz Sosa, O. Sentieys, C. Roland. A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment. Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct 2018, Torino, Italy. pp.1-8

Shacham, K. Bergman, and L. P. Carloni. "Photonic networks-on-chip for future generations of chip multiprocessors." IEEE Transactions on Computers, vol. 57.9 pp: 1246-1260, 2008.

Luo, C. Killian, D. Chillet, S. Le Beux, I. OConnor, O. Sentieys. “Offline optimization of wavelength allocation and laser power in nanophotonic interconnects”. In: ACM Journal on Emerging Technologies in Computing Systems (JETC) (2018).

Pasricha, J. Jose and S. Deb, "Electronic, Wireless, and Photonic Network- on-Chip Security: Challenges and Countermeasures," in IEEE Design & Test, vol. 39, no. 6, pp. 90-98, Dec. 2022, doi: 10.1109/MDAT.2022.3203017.

Main activities

We seek to find systematic methods to answer the key questions:

What are the main weaknesses on emerging on-chip interconnect such as ONoC or WiNoC?

How to detect and locate attacks on emerging on-chip interconnects?

How to improve the robustness against security threats?

Skills

Expected profile of the candidates:

PhD in Computer Science, Electrical or Computer Engineering.

Strong background Security, multi/manycore architectures, on-chip interconnects.

Familiarity with manycore simulator is greatly appreciated.

Programming experience, e.g., in C/C++ and Python.

Good knowledge of computer architecture, hardware design, and embedded systems.

Benefits package

Subsidized meals

Partial reimbursement of public transport costs

Possibility of teleworking (90 days per year) and flexible organization of working hours

Partial payment of insurance costs

Remuneration

monthly gross salary amounting to 2746 euros

General Information

Theme/Domain : Architecture, Languages and Compilation Scientific computing (BAP E)

Town/city : Lannion

Inria Center : Centre Inria de l'Université de Rennes

Starting date : 2023-05-31

Duration of contract : 1 year

Deadline to apply : 2023-04-25

Contacts

Inria Team : TARAN

Recruiter : Killian Cédric / [email protected]

The keys to success

What is valued the most is autonomy. We expect the postdoc to be motivated and capable of composing short and mid-term objectives themselves.

About Inria

Inria is the French national research institute dedicated to digital science and technology. It employs 2,600 people. Its 200 agile project teams, generally run jointly with academic partners, include more than 3,500 scientists and engineers working to meet the challenges of digital technology, often at the interface with other disciplines. The Institute also employs numerous talents in over forty different professions. 900 research support staff contribute to the preparation and development of scientific and entrepreneurial projects that have a worldwide impact.

Instruction to apply

Please submit online : your resume, cover letter and letters of recommendation eventually

For more information, please contact [email protected]

Defence Security : This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment.

Recruitment Policy : As part of its diversity policy, all Inria positions are accessible to people with disabilities.

Warning : you must enter your e-mail address in order to save your application to Inria. Applications must be submitted online on the Inria website. Processing of applications sent from other channels is not guaranteed.