Post-Doctoral Research Visit F/M Fault Tolerant Emerging On-Chip Interconnects

April 25, 2023
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2023-05732 - Post-Doctoral Research Visit F/M Fault Tolerant Emerging On- Chip Interconnects

Contract type : Fixed-term contract

Renewable contract : Oui

Level of qualifications required : PhD or equivalent

Fonction : Post-Doctoral Research Visit

About the research centre or Inria department

The Inria Rennes - Bretagne Atlantique Centre is one of Inria's eight centres and has more than thirty research teams. The Inria Center is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc


This postdoc position will be funded by the Rakes and AllOpticall2 ANR Projects.

These projects involve Inria Taran (Rennes/Lannion), INL (Lyon), Lab-STICC (Lorient), and TIMA (Grenoble).

The Taran team has already a strong background in on-chip interconnects, and on the emerging interconnect paradigms (WiNoC, ONoC) targeted in this project.



Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for high-performance embedded computing systems and HPC.

In the last decade, electrical Network-on-Chips (ENoCs) have emerged as an efficient solution for multicore architectures, in the range of tens of cores on a-chip, to circumvent the parallelism limitations of traditional buses. Nevertheless, as the manycore era progresses, ENoCs suffer from scalability in terms of latency and energy due to a huge increase on the number of hops between cores 1, 2, hence emerging technologies are called to supplement this traditional interconnect.

In parallel, technology evolution has allowed for the integration of silicon photonics and wireless communications on chip, thus leading to the Wireless Network-on-Chip (WiNoC) 3-4 and Optical Network-on-Chip (ONoC) 5-6 paradigms. These emerging technologies are showing significant advantages for broadcasting data (WiNoC) and low-latency communications (ONoC), whereas conventional Electrical Network-on-Chip (ENoC) is reaching its limit 1. For future on-chip interconnect, it seems clear that the use of just one technology will lead to inefficient solutions, hence hybrid NoCs are using, which is a combination of two technologies.

However, disruptive technologies suffer from higher variability due to still maturing fabrication process . This prevents from their deployment, which calls for optimization methods and dedicated fault-tolerant hardware designs to improve their robustness. Moreover, as we approach the limit of CMOS scaling, it becomes increasingly unlikely for a computing device to be fully functional due to various sources of faults, especially in harsh environment such as in space 7.

This call to provide fault tolerant techniques to enhance robustness or to limit fault impacts on error resilient applications , e.g. neural networks or approximate computing 8, that is executed on emerging on-chip interconnects.

The scope of the PostDoc position is relatively open and applicants are expected to identify the direction that suits them the most as a function of their background and interest.

Main activities

The goal is to improve the fault-tolerance of emerging on-chip interconnects in the context of manycore architectures, and we seek to find systematic methods to answer the key questions:

  • How to analysis the reliability of emerging interconnect and to detect/localize faults?
  • How to improve the robustness of emerging interconnect?
  • How to continue to use faulty emerging on-chip interconnect for instance in the context of error tolerant applications?
  • Skills

    Expected profile of the candidates:

  • PhD in Computer Science, Electrical or Computer Engineering
  • Strong background in Fault Tolerance, multi/manycore architectures, on- chip interconnects
  • Familiarity with manycore simulator is greatly appreciated.
  • Programming experience, e.g., in C/C++ and Python.
  • Good knowledge of computer architecture, hardware design, and embedded systems.

    Benefits package
  • Subsidized meals
  • Partial reimbursement of public transport costs
  • Possibility of teleworking (90 days per year) and flexible organization of working hours
  • Partial payment of insurance costs
  • Remuneration

    monthly gross salary amounting to 2746 euros

    General Information
  • Theme/Domain : Architecture, Languages and Compilation Scientific computing (BAP E)

  • Town/city : Lannion

  • Inria Center : Centre Inria de l'Université de Rennes
  • Starting date : 2023-05-01
  • Duration of contract : 1 year, 1 month
  • Deadline to apply : 2023-04-25
  • Contacts
  • Inria Team : TARAN
  • Recruiter : Killian Cédric / [email protected]
  • The keys to success

    What is valued the most is autonomy. We expect the postdoc to be motivated and capable of composing short and mid-term objectives themselves.

    About Inria

    Inria is the French national research institute dedicated to digital science and technology. It employs 2,600 people. Its 200 agile project teams, generally run jointly with academic partners, include more than 3,500 scientists and engineers working to meet the challenges of digital technology, often at the interface with other disciplines. The Institute also employs numerous talents in over forty different professions. 900 research support staff contribute to the preparation and development of scientific and entrepreneurial projects that have a worldwide impact.

    Instruction to apply

    Please submit online : your resume, cover letter and letters of recommendation eventually

    For more information, please contact [email protected]

    Defence Security : This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment.

    Recruitment Policy : As part of its diversity policy, all Inria positions are accessible to people with disabilities.

    Warning : you must enter your e-mail address in order to save your application to Inria. Applications must be submitted online on the Inria website. Processing of applications sent from other channels is not guaranteed.

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