Post-Doctoral Research Visit F/M Enhancing cache coherence protocols with emerging interconnect technologies

Inria

France

September 30, 2022

Description

2022-05303 - Post-Doctoral Research Visit F/M Enhancing cache coherence protocols with emerging interconnect technologies

Contract type : Fixed-term contract

Renewable contract : Oui

Level of qualifications required : PhD or equivalent

Fonction : Post-Doctoral Research Visit

About the research centre or Inria department

The Inria Rennes - Bretagne Atlantique Centre is one of Inria's eight centres and has more than thirty research teams. The Inria Center is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc.

Context

This postdoc position will be funded by the Rakes and AllOpticall2 ANR Projects.

These projects involve Inria Taran (Rennes/Lannion), INL (Lyon), Lab-STICC (Lorient), TIMA (Grenoble), CEA (Paris-Saclay), and C2N (Paris- Saclay).

The Taran team has already a strong background in on-chip interconnects, and on the emerging interconnect paradigms (WiNoC, ONoC) targeted in this project.

Assignment

Subject

Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for high-performance embedded computing systems and HPC.

These parallelism capabilities obviously generate an enormous amount of data exchanges making the communication medium a key element of the overall performance of the system. However, because of the difference of speed between the processors and the main memory, fast and small dedicated hardware- controlled memories containing copies of parts of the main memory (a.k.a caches) are used 1. To keep these distributed copies up-to-date and synchronize the accesses to shared data, it requires to share information between some may if not all the nodes. This leads to increase the number of data transfers that must be supported by the interconnection media. Furthermore, these specific data transfers concern generally one source and several destinations, which correspond to multicast/broadcast communications.

In parallel, technology evolution has allowed for the integration of silicon photonics and wireless communications on chip, thus leading to the Wireless Network-on-Chip (WiNoC) 2-3 and Optical Network-on-Chip (ONoC) 4-5 paradigms. These emerging technologies are showing significant advantages for broadcasting data (WiNoC) and low-latency communications (ONoC), whereas conventional Electrical Network-on-Chip (ENoC) is reaching a limit 6.

In this context, the main objective of this project is to explore how these emerging technologies can improve the efficiency of on-chip interconnection systems of shared-memory manycore architectures based on cache coherence protocols. We will study new cache protocols which are well adapted for the specific properties of hybrid interconnects. Model of communications for each media/technology will be defined, in terms of data transfer latency, power consumption, etc., and these models will be used at the operating system level to select the best media for each type of transfer.

Bibliography:

  • M. MK Martin, M. D. Hill, and D. J. Sorin. "Why on-chip cache coherence is here to stay." Communications of the ACM 55.7 (2012): 78-89.
  • A. Karkar et al. “A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many- Cores”. In: IEEE Circuits and Systems Magazine 16., pp. 58–72 , 2016.
  • M. F. Chang, et al., “CMP Network-on-Chip Overlaid with Multi-Band RF-Interconnect,” Proc. of IEEE Int. symposium on High- Performance Computer Architecture (HPCA), pp. 191-202, 2008.
  • A. Shacham, K. Bergman, and L. P. Carloni. "Photonic networks-on-chip for future generations of chip multiprocessors." IEEE Transactions on Computers, vol. 57.9 pp: 1246-1260, 2008.
  • J. Ortiz Sosa, O. Sentieys, C. Roland. A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment. Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) , Oct 2018, Torino, Italy. pp.1-8
  • J. Luo, C. Killian, D. Chillet, S. Le Beux, I. OConnor, O. Sentieys. “Offline optimization of wavelength allocation and laser power in nanophotonic interconnects”. In: ACM Journal on Emerging Technologies in Computing Systems (JETC) (2018).
  • Main activities

    The scope of the PostDoc position is relatively open and applicants are expected to identify the direction that suits them the most as a function of their background and interest. The goal is to improve performance and energy efficiency of on-chip interconnect in the context of manycore architectures, and we seek to find systematic methods to answer the key questions:

  • How emerging interconnect can influence the classic cache coherency protocols?
  • Can efficient broadcast offered by WiNoC and low-latency of ONoC be leveraged to improve on-chip interconnect performance?
  • Can we provide new cache coherency protocols taking advantage of emerging interconnect technologies?
  • Skills
  • PhD in Computer Science, Electrical or Computer Engineering.
  • Strong background in cache coherency protocols, multi/manycore architectures, on-chip interconnects, NoCs.
  • Familiarity with gem5 simulator is greatly appreciated.
  • Programming experience, e.g., in C/C++ and Python.
  • Good knowledge of computer architecture, hardware design, and embedded systems.
  • Benefits package
  • Subsidized meals
  • Partial reimbursement of public transport costs
  • Possibility of teleworking (90 days per year) and flexible organization of working hours
  • Partial payment of insurance costs
  • Remuneration

    Monthly gross salary amounting to 2746 euros

    General Information
  • Theme/Domain : Architecture, Languages and Compilation Scientific computing (BAP E)

  • Town/city : Lannion

  • Inria Center : CRI Rennes - Bretagne Atlantique
  • Starting date : 2022-12-01
  • Duration of contract : 1 year, 6 months
  • Deadline to apply : 2022-09-30
  • Contacts
  • Inria Team : TARAN
  • Recruiter : Killian Cédric / cedric.killian@irisa.fr
  • The keys to success

    What is valued the most is autonomy. We expect the postdoc to be motivated and capable of composing short and mid-term objectives themselves.

    About Inria

    Inria is the French national research institute dedicated to digital science and technology. It employs 2,600 people. Its 200 agile project teams, generally run jointly with academic partners, include more than 3,500 scientists and engineers working to meet the challenges of digital technology, often at the interface with other disciplines. The Institute also employs numerous talents in over forty different professions. 900 research support staff contribute to the preparation and development of scientific and entrepreneurial projects that have a worldwide impact.

    Instruction to apply

    Please submit online : your resume, cover letter and letters of recommendation eventually

    Defence Security : This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment.

    Recruitment Policy : As part of its diversity policy, all Inria positions are accessible to people with disabilities.

    Warning : you must enter your e-mail address in order to save your application to Inria. Applications must be submitted online on the Inria website. Processing of applications sent from other channels is not guaranteed.