Phd Student Position In Electrical Engineering

Universities and Institutes of France

France

June 30, 2022

Description

  • Organisation/Company: Institut d'Electronique Microélectronique et de Nanotechnologies
  • Research Field: Engineering › Electrical engineering
  • Researcher Profile: First Stage Researcher (R1)
  • Application Deadline: 30/06/2022 17:00 - Europe/Brussels
  • Location: France › Lille
  • Type Of Contract: Temporary
  • Job Status: Full-time
  • Hours Per Week: 40
  • Offer Starting Date: 03/10/2022
  • Process optimization towards the development of vertical GaN on Silicon transistors

  • Context and objectives
  • The interest of GaN-based devices for power electronics has significantly increased in recent years. The properties related to the large gap of GaN material enable an excellent trade-off between the on-state resistance (Ron) and the breakdown voltage (BV). Moreover, recent advances in the growth of GaN on silicon (111) substrate allow for future integration of low-cost high-power devices with mature technologies such as CMOS. Nevertheless, GaN power transistors are currently based on lateral HEMTs for which higher voltage operation is obtained by increasing the gate and drain spacing, to the detriment of current and power density. To date, GaN transistors are mostly lateral HEMTs and Schottky diodes using AlGaN/GaN heterostructures. Although fabricated on large and low-cost silicon substrates, these components have many limitations such as a too low threshold voltage VTH (issue related to immunity to electromagnetic disturbances), limited voltage operation (< 1 kV) and a clear trade-off with the power density. In addition, these lateral components are sensitive to surface charge effects, degrading the dynamic the on-state resistance.

    This is the reason why it is essential to fabricate vertical GaN devices that can potentially withstand higher voltages (> 1 kV) while maintaining a small fingerprint. The vertical geometry enables higher current density and voltage (beyond 1000 V, with 50 A rated chips) that can be obtained with thicker layers. Vertical GaN devices have already been introduced at the industrial level, but all based on bulk GaN substrates. This substrate is both expensive and limited in thermal performance. Therefore, two paths will be explored within this PhD thesis: GaN on sapphire substrate on which the epi-growth is easier to control and GaN on silicon which presents more risks on the epi- stack quality but is closer to industrial objectives.

    The use of heteroepitaxy for the development of vertical transistors requires a backside substrate etching. After the front side processing, the wafer can be temporarily transferred to a carrier (e.g. glass) in order to mechanically stabilize the devices and thus allow processing on the backside. In the frame of a European H2020 project, we have managed to overcome the problem of parasitic conduction under high electric fields by means of a local substrate backside etching, specifically around the transistors. This technological innovation on an optimized epitaxy layer configuration allowed us to demonstrate a unique combination of breakdown voltage beyond 2000 V associated with an on-state resistance of less than 2 mΩcm2. For vertical GaN transistors, the objective is to form the drain ohmic contact directly on the active layer by etching both the substrate and the buffer layers.

    This PhD thesis work is part of a project called VERTIGO within the PEPR Electronics, which aims to develop gallium nitride power transistors in vertical configuration. In this context, the candidate will work within IEMN platforms on the optimization of technological processes for the development of vertical GaN transistors on sapphire while epilayers will be provided by CRHEA laboratory. The realization of simplified pseudo-vertical test vehicles will allow rapid development and analysis of different technological approaches. The candidate will also work on the development of GaN-on-Silicon devices and more specifically on the backside processing by applying a local substrate removal on devices supplied by CEA LETI. The integration aspects will be taken into account and discussed with the project partners.

    Part of the work will be carried out at the premises of project partners such as CRHEA for the material growth, CEA LETI for the fabrication process or AMPERE for electrical characterization.

  • Research programme
  • The thesis work program will be defined as follows:

  • Literature survey
  • Definition of devices to be fabricated in collaboration with the partners;
  • Optimization of the existing process flow including front side and backside of GaN power devices developed at IEMN. For the backside processing of devices on Silicon, the PhD candidate will use the membrane technology developed at IEMN allowing a preliminary characterization of vertical transistors;
  • Complete systematic characterization at IEMN and Ampère in DC, dynamic, high voltage and temperature regimes in order to validate the integrity of the produced devices.

  • Laboratory description

  • IEMN is a large research center in Micro and Nanotechnologies including in a single structure the bulk of regional research in a vast scientific field ranging from nanosciences to instrumentation. Working together researchers with different cultures, approaches and motivations, building a continuum of knowledge from fundamental problems to applications is what makes us special today. Today, nearly 500 people, including a hundred international researchers, work together. The core of our activities is focused on micro and nanotechnologies and their applications in the fields of information, communication, transport and health. Our researchers have at their disposal exceptional experimental resources, in particular technology and characterization facilities whose capabilities and performance are at the highest European level. IEMN is part of the RENATECH network of large technology centers. RENATECH. Our scientific policy consists not only in the deepening of knowledge but also to the establishment of a privileged partnership with industrial leaders in their markets and the development of a close partnership with regional SMEs and start-ups from the IEMN.

    Offer Requirements
  • REQUIRED EDUCATION LEVEL
  • Engineering: Master Degree or equivalent

  • REQUIRED LANGUAGES
  • FRENCH: Good

    Contact Information
  • Organisation/Company: Institut d'Electronique Microélectronique et de Nanotechnologies
  • Department: Wide Bandgap Group - WIND
  • Organisation Type: Research Laboratory
  • Website: https: // www. iemn.fr/la-recherche/les-groupes/groupe-wind
  • E-Mail: farid.medjdoub@iemn.fr
  • Country: France
  • City: Lille
  • Street: Avenue poincare
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